The present invention generally relates to the design of integrated circuits, and more particularly, to a method for improving a floorplanning layout that provides electrostatic discharge (ESD) robustness to an Application Specific Integrated Circuit (ASIC) design system.
It is known in the art that electrostatic discharge protect devices, such as ESD clamps, connected to integrated circuit (IC) chip input/output (I/O) pads protect circuits from ESD damage. ESD damage typically results from an ESD between any two chip pads. Conventional ESD clamps were designed and located based on well understood requirements of the particular circuit or cell and the physical characteristics of the chip technology and the ESD clamp. Thus, for a single power supply chip, the ESD clamp is typically a pair of reverse biased diodes, each connected between the supply or its return line (ground) and an IC chip signal pad.
The level of protection afforded by prior art ESD clamps is determined by the pad to ESD clamp wiring and the circuit attached to the pad. The design objective is to insure that the ESD clamp turns on prior to the circuit or wiring to the circuit failing. Thus, wiring between the pad and the ESD clamp must be sufficiently wide to transfer the charge to the clamp without failing during the transfer. However, even for a wide wire, if its resistance is too high due to its length, the combination of the resistance and wiring added to the ESD clamp capacitance filters the charge provided to the ESD clamp, reducing its effectiveness. Under certain circumstances, the wiring resistance in the I/O net wiring acts as a voltage divider. If the pad to clamp resistance is too high, the voltage dropped across the divider resistance may prevent the clamp from ever turning on.
Referring to FIG. 1, there is shown a schematic diagram illustrating a resistive network of the power grid model connecting I/O cell 60 and ESD clamp 70 to the chip power grid 50. The resistive network is a linearized current-voltage model as used by an ESD analysis program to detect occurrences of pad to clamp resistances that may inhibit the proper functioning of the ESD clamp. For each ESD clamp device, a voltage source 20 and a series resistor 25 are inserted into the network. During analysis, a current from a simulated Charged Device Model (CDM) discharge is inserted (ESD_CUR 30). The ESD analysis program uses the current to analyze the voltage drop 10 due to the resistance across the power bus from I/O power pin 40 to the chip power grid 50, and flags a voltage drop that is greater than a predetermined limit (ESD_LIMIT).
With the shrinking of technology scaling from 130 nm to 90 nm and beyond, a new level of challenge is introduced to achieve adequate protection against electrostatic discharge (ESD) for CMOS integrated circuits. Technology scaling has brought with it very low breakdown voltages in CMOS circuits. In the 90 nm node, these breakdown voltages fall below 10 V for transient stresses of short duration as it typically occurs in a Charged Device Model (CDM) discharge. A CDM event happens when a device becomes charged (e.g., by sliding down a feeder) and discharged by coming into contact with a conductive surface. A rapid discharge occurs from the device to the conductive object.
At the same time, advances in IC technology have increased the circuit density which has led to a corresponding increase in the number of pads for off-chip connections, i.e., for chip input/outputs (I/Os) and for supplying power and ground to the chip according to what is well known in the art as Rent's Rule.
A 90 nm ASIC design system typically handles in excess of 1500 I/Os and in excess of 200 analog and high speed serial cores. The problem is even more challenging than in previous technologies due to the shear quantity of I/Os and cores, design system complexity, and the number of tape-outs, as described, e.g., by Ciaran J. Brennan, Joseph Kozhaya, Robert Proctor, Jeffrey Sloan, Shunhua Chang, James Sundquist, Terry Lowe, in an article entitled “ESD Design Automation for a 90 nm ASIC Design System”, published in the Proceedings of the 26th EOS/ESD Symposium, 2004.
In an ASIC environment, many aspects of the design must be automated at the cell and chip level to achieve the necessary efficiency and quick turn-around-time (TAT) needed to support high volume of tape-outs. As a result, it becomes necessary to increase the level of design automation for ESD to ensure adequate protection against ESD failures such that they do not adversely affect the TAT of ASIC chips.
The aforementioned problem is not novel. Several approaches have been proposed, as for instance, in U.S. Pat. No. 6,725,439, that describes a method of providing ESD protection to an integrated circuit (IC) chip. Placing maximum resistance and minimum wire width constraints on I/Os and ESD signal nets ensures ESD protection when all the I/O-to-chip-pad routing constraints are satisfied. The design tools adhering to these routing constraints also verify that all the I/O-to-chip-pad routing constraints are met. Further, checking is performed to secure that the power supply and ground lines are properly connected to ESD clamps. However, the methodology described therein fails to optimize the I/O placement to meet ESD power supply targets. Neither does it place I/Os in close proximity of each other to share local power bus connections. Thus, the method described checks for the length and width constraints on the I/O to ESD connections, and fails to solve the problem associated with ESD placement.
U.S. patent application Ser. No. 10/711,633 describes a method for accurately and efficiently checking the electrical chip-level power to guarantee the ESD reliability of VLSI ASIC chips. Further described is an ESD book placement scheme wherein the chip is divided into sections, an ESD book is placed at the “center of mass” thereof, and an ESD verification is performed to determine whether all the I/Os meet predetermined ESD targets. Provisions are made to eliminate any I/Os failing to achieve the stated targets due to unsatisfactory placement or wiring. If I/Os are found not to meet the targets in a given section, the ESD book is removed. The section is then subdivided into smaller sections, placing the ESD book in each section, and repeating the check. The process of subdividing continues until all the I/Os are accounted for. Further discussed is a method for performing an ESD check by applying a current, calculating the voltage drop, and comparing it to a predetermined limit. The method begins by placing all I/Os and creating an ESD placement solution. Some of the I/O cells may fail ESD because they rely on power routing to the chip power grid on last metal from both I/O and ESD cells. The cited reference does not discuss I/O placements nor the process for optimizing the I/O placement to meet ESD targets. Neither are discussed providing local connections between nearby I/Os, nor placing an ESD book having local connections to the I/Os.
Thus, there is a need in industry to provide integrated circuits with a robust ESD protection, and for a method and a system for designing chips and ASICs that optimally place the I/Os meeting stringent ESD targets.